Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu F2MC-16LX Hardware Manual

6.3

Low-Power Consumption Mode Control Register (LPMCR)

The low-power consumption mode control register (LPMCR) performs functions
including changing the current mode to the low-power consumption mode, canceling
from the low-power consumption mode, and specifying the number of CPU-clock
pause cycles in the CPU intermittent operation mode.
I Low-power consumption mode control register (LPMCR)
Figure 6.3-1 "Configuration of low-power consumption mode control register (LPMCR)" shows
the configuration of the low-power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of low-power consumption mode control register (LPMCR)
Address
bit15
0000A0
H
R/W : Read/write enabled
W : Write only
: Initial value
bit8 bit7 bit6 bit5
(CKSCR)
STP SLP SPL
W W R/W
CHAPTER 6 LOW-POWER CONSUMPTION MODE
bit4 bit3 bit2 bit1 bit0
RST TMD CG1 CG0
Reserved
W R/W R/W R/W R/W
Reserved Reserved bit
Reading and writing has no effect on operation
CG1 CG2
Bit for number of CPU-clock pause cycles
0 0 0 cycle (CPU clock = Resource clock)
8 cycles (CPU clock: Resource clock =
0 1
1: About 3 to 4)
16 cycles (CPU clock: Resource clock =
1 0
1: About 5 to 6)
32 cycles (CPU clock: Resource clock =
1 1
1: About 9 to 10)
TMD Clock mode or timebase timer mode bit
0 Change to timebase timer mode
1 No change, no effect on others
RST Internal reset signal generator bit
0 Generates an internal reset signal of 3 machine cycles
1 No change, no effect on others
Pin state specification bit (in watch and timebase
SPL
timer stop modes)
0 Hold
1 High impedance
SLP Sleep mode bit
0 No change, no effect on others
1 Change to sleep mode
Stop mode bit
STP
0 No change, no effect on others
1 Change to stop mode
Initial value
00011000
B
133