Low-Power Consumption Mode Control Register (Lpmcr); Fig. 5.3 Configuration Of Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu MB90420/5 (A) Series Hardware Manual

5.3 Low-power Consumption Mode Control Register (LPMCR)

The low-power consumption mode control register (LPMCR) transits/cancels the low-power consumption
mode and sets the CPU suspended clock count in the CPU intermittent operation mode.
n Low-power consumption mode control register (LPMCR)
Figure 5.3 shows the configuration of the low-power consumption mode control register (LPMCR).
Address
bit 15
0000A0
(CKSCR)
H
R/W : Both read and write
R : Write only
: Initial value

Fig. 5.3 Configuration of Low-power Consumption Mode Control Register (LPMCR)

LOW-POWER CONSUMPTION MODE
bit 8 bit 7 bit 6 bit 5 bit 4
STP SLP SPL RST TMD CG1 CG0 RESV
W W R/W
RESV
CG1
0
0
1
1
TMD
0
1
RST
0
1
SPL
0
1
SLP
0
1
STP
0
1
bit 3 bit 2 bit 1 bit 0
W R/W R/W R/W R/W
Always write 1 to this bit.
CG0 CPU Suspended Clock Count Select Bit
0 0 clock (CPU clock = resource clock)
1 8 clocks (CPU clock: resource clock = 1: about 3 to 4)
0 16 clocks (CPU clock: resource clock = 1: about 5 to 6)
1 32 clocks (CPU clock: resource clock = 1: about 9 to 10)
Time-base Timer Mode Bit
Transition to time-base timer mode
Writing 1 to this bit does not affect operation.
Internal Reset Signal Generate Bit
Internal reset signal of 3 machine cycles generated
Writing 1 to this bit does not affect operation.
Pin State Specification Bit
(when time-base timer, timer or stop mode)
Hold
High impedance
Writing 0 to this bit does not affect operation.
Transition to sleep mode
Writing 0 to this bit does not affect operation.
Transition to stop mode
5-7
Initial value
00011000
B
Reserved Bit
Sleep Bit
Stop Bit