Table 3.7-10 Low-Power Consumption Mode Settings In Standby Control Register (Stbc) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
Writing to the watch bit (TMD) is ignored during operation in main clock mode.
Table 3.7-10 Low-power Consumption Mode Settings in Standby Control Register
(STBC)
STP (bit 7)
Oscillation Stabilization Delay Time
Both in the main clock and the subclock modes, the oscillator that provides the source
oscillation is stopped during stop mode. Thererfore, a delay time is required for oscillation to
stabilize after the oscillator restarts operation.
To wait until oscillation becomes stable, the CPU takes the main clock oscillation stabilization
delay time (selected from four types) produced by the timebase timer in main clock mode. In
subclock mode, the CPU takes the subclock oscillation stabilization delay time produced by the
watch prescaler.
If the interval time set for the timebase timer is less than the oscillation stabilization delay time in
the main clock mode, the timebase timer generates an interval timer interrupt request before the
end of the oscillation stabilization delay time. To prevent this in the main clock mode, disable the
interrupt request output for the timebase timer (TBTC: TBIE = "0") before changing to stop mode
as necessary.
Similarly, selecting the specified interrupt interval time for the watch prescaler generates a
watch interrupt request. Disable the watch interrupt request output for the watch prescaler
(WPCR: WIE=0) as necessary before changing to stop mode during subclock mode.
94
STBC register
SLP (bit 6)
0 0
0 0
0 1
1 0
TMD (bit 3)
0
1
0
0
Mode
Normal
Watch
Sleep
Stop