ST STM32G0 1 Series Reference Manual page 1294

Universal serial bus full-speed host/device interface (USB)
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 ERR_RX: Received error for an IN transaction
– Host mode
Bit 25 ERR_TX: Received error for an OUT/SETUP transaction
– Host mode
Bit 24 LS_EP: Low speed endpoint – host with HUB only
– Host mode
Bit 23 NAK:
– Host mode
Bits 22:16 DEVADDR[6:0]:
– Host mode
1294/1390
This bit is set by the hardware when an error (for example no answer by the device, CRC
error, bit stuffing error, framing format violation, etc.) has occurred during an IN transaction
on this channel. The software can only clear this bit. If the ERRM bit in USB_CNTR register
is set, a generic interrupt condition is generated together with the channel related flag, which
is always activated.
This bit is set by the hardware when an error (for example no answer by the device, CRC
error, bit stuffing error, framing format violation, etc.) has occurred during an OUT or SETUP
transaction on this channel. The software can only clear this bit. If the ERRM bit in
USB_CNTR register is set, a generic interrupt condition is generated together with the
channel related flag, which is always activated.
This bit is set by the software to send an LS transaction to the corresponding endpoint.
0: Full speed endpoint
1: Low speed endpoint
This bit is set by the hardware when a device responds with a NAK. Software can use this bit
to monitor the number of NAKs received from a device.
Device address assigned to the endpoint during the enumeration process.
RM0444 Rev 5
RM0444