Configuration Flow Diagram - Intel Agilex Configuration User Manual

2. Intel Agilex Configuration Details
UG-20205 | 2019.04.03

2.2. Configuration Flow Diagram

This topic describes the configuration flow for Intel Agilex devices.
Figure 5. Intel Agilex FPGA Configuration Flow
Power-On
Power Up
• The Intel Agilex power supplies power following the guidelines in the Power-Up Sequence Requirements for Intel Agilex
Devices section of the Intel Agilex Power Management User Guide.
• A device-wide power-on reset (POR) asserts after the power supplies reach the correct operating voltages. The external
power supply ramp must not be slower than the minimum ramping rate until the supplies reach the operating voltage.
• The
SDM_IO0
a weak high.
Send Feedback
Configuration Pass Flow
Configuration Fail Flow
Reconfiguration Flow
nCONFIG = LOW
SDM
Startup
*FPGA first mode, fabric configuration begins immediately.
HPS first mode, HPS configures the fabric.
**1 MS 50% when SDM operates from bootROM code.
, , and pins remain low internally. Internal circuitry pulls the remaining
SDM_IO8 SDM_IO16
nSTATUS = HIGH
Device
Clean
nCONFIG = LOW
nSTATUS = LOW nCONFIG = LOW
nCONFIG
SDM
= HIGH
Idle
Firmware
nCONFIG = HIGH
nSTATUS= HIGH
nSTATUS = LOW
±
nCONFIG = LOW nCONFIG = LOW
CONF_DONE
FPGA
User
= HIGH
Config*
Mode
nSTATUS = LOW Pulse**
nCONFIG = HIGH
nSTATUS= HIGH
CONF_DONE = HIGH
Fail FPGA
INIT_DONE= HIGH
Config
SDM_IO
Intel ® Agilex ™ Configuration User Guide
pins to
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