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Debug support (DBG)
CTI channel out status register (CTI_CHOUTSTSR)
Address offset: 0x13C
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CHOUTSTATUS[3:0]: channel output status
There is one bit of the register for each channel output. When a bit is set to 1, it indicates that
the corresponding channel output is active. When it is set to 0, the corresponding channel
output is inactive.
CTI channel gate register (CTI_GATER)
Address offset: 0x140
Reset value: 0x0000 000F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 GATEEN[3:0]: channel output enable
For each channel, defines whether an event on that channel can propagate over the CTM to
other CTIs.
0000: Channels events do not propagate.
XXX1: Channel 0 events propagate.
XX1X: Channel 1 events propagate.
X1XX: Channel 2 events propagate.
1XXX: Channel 3 events propagate.
1360/1450
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 5
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
CHOUTSTATUS[3:0]
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
GATEEN[3:0]
rw
rw
rw
rw
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