STMicroelectronics STM32WL5 Series Reference Manual page 1344

Debug support (DBG)
38.6.11 DWT function register x (DWT_FUNCTxR)
Address offset: 0x028 + 0x010 * x, (x = 0 to 3)
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
DATAVADDR0[3:0]
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 MATCHED: comparator match (read only)
Indicates if a comparator match has occurred since the register was last read.
0: No match
1: Match occurred
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 DATAVADDR1[3:0]: When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold
the comparator number of a second comparator to use for linked address comparison.
Bits 15:12 DATAVADDR0[3:0]: When the DATAVMATCH and LNK1ENA bits are both 1, this field can hold
the comparator number of a comparator to use for linked address comparison.
Bits 11:10 DATAVSIZE[1:0]: For data value matching, specifies the size of the required data comparison.
0x0: Byte
0x1: Half word
0x2: Word
0x3: reserved
Bit 9 LNK1ENA: enable for a second linked comparator
Indicates whether use of a second linked comparator is supported (read only).
0x1: Supported
Bit 8 DATAVMATCH: enable for cycle comparison.
0x0: Address comparison
0x1: Data value comparison
Bit 7 CYCMATCH: enable for cycle count comparison on comparator 0
This field is reserved for other comparators.
0x0: No cycle count comparison
0x1: Compares DWT_COMP0R with the cycle counter, DWT_CYCCNTR.
Bit 6 Reserved, must be kept at reset value.
1344/1450
28 27 26 25
Res. Res. Res.
12 11 10 9
LNK1E
DATAVSIZE[1:0]
NA
rw rw rw rw
24 23 22
MATCH
Res. Res.
ED
r
8 7 6
DATAV CYCM EMITR
Res.
MATCH ATCH ANGE
rw rw
RM0453 Rev 5
21 20 19 18
Res. Res. DATAVADDR1[3:0]
rw rw
5 4 3 2
Res. FUNCTION[3:0]
rw rw rw
RM0453
17 16
rw rw
1 0
rw rw