STMicroelectronics STM32WL5 Series Reference Manual page 1347

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
38.6.16
DWT CoreSight peripheral identity register 3 (DWT_PIDR3)
Address offset: 0xFEC
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications
38.6.17
DWT CoreSight component identity register 0 (DWT_CIDR0)
Address offset: 0xFF0
Reset value: 0x0000 000D
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]
0x0D: Common ID value
38.6.18
DWT CoreSight peripheral identity register 1 (DWT_CIDR1)
Address offset: 0xFF4
Reset value: 0x0000 00E0
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
REVAND[3:0]
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
CLASS[3:0]
r
r
RM0453 Rev 5
Debug support (DBG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
CMOD[3:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PREAMBLE[7:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
PREAMBLE[11:8]
r
r
r
r
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
r
r
1347/1450
1435

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