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TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
timing requirements for interrupt response cycles
NO
NO.
2
t
w(ILOW)
3
t
w(IHIGH)
†
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions during interrupt response
§
cycles
(see Figure 29)
NO.
NO
1
t
d(EINTH-IACKH)
4
t
d(CKO2L-IACKV)
5
t
d(CKO2L-INUMV)
6
t
d(CKO2L-INUMIV)
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
CLKOUT2
2
EXT_INTx, NMI
Intr Flag
IACK
INUMx
46
EXTERNAL INTERRUPT TIMING
Width of the interrupt pulse low
Width of the interrupt pulse high
PARAMETER
PARAMETER
Delay time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
3
Figure 29. Interrupt Timing
POST OFFICE BOX 1443
†‡
(see Figure 29)
1
5
Interrupt Number
•
HOUSTON, TEXAS 77251--1443
- -200
MIN
MAX
2P
2P
- -200
MIN
MAX
9P
--4
--4
4
4
UNIT
UNIT
ns
ns
UNIT
UNIT
ns
6
ns
6
ns
ns
6
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