Asynchronous Read With Multiplexed Address And Data Memory - Texas Instruments OMAP5912 Reference Manual

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Asynchronous 16-Bit Read Operation with Ready. RDWST=2 FCLKDIV=0

OESETUP = 0 OEHOLD = 0 ADVHOLD = 0. Data write-back on the bus after read

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

Asynchronous Read With Multiplexed Address and Data Memory

OMAP3.2 Subsystem

active and depending on REF_CLK frequency, a minimum RDWST value

may be needed for the FLASH.RDY state to be correctly monitored by the

As an example, a minimum of RDWST = 2 is needed for a nonready

device that drives FLASH.RDY low with 0 time delay from CS low and

for a CS configuration FCLKDIV = 0.

See the OMAP5912 Data Manual (SWPS012) for timing information

regarding FLASH.RDY assertion timing constraint.

The EMIFS can support multiplexed address and data memory devices

without adding external logic. Multiplexed mode is enabled when the MAD

bit field in the EMIFS CS configuration register is set to 1 (see Table 19).

The following figure shows an asynchronous read operation with

multiplexed address/data bus.

Valid address

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