Synchronous Read In Multiplexed Address And Data Memory - Texas Instruments OMAP5912 Reference Manual

Traffic Controller
Figure 23. Mode 5 Synchronous Burst 2x16-Bit Read Operation on 16-Bit Width Device
(RDWST=3, FCLKDIV =0, ADVHOLD=0, RDMODE=5). Data write-back on the bus after
read completion
TC_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A(25:1)
FLASH.D(15:0)
FLASH.OE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY

Synchronous Read in Multiplexed Address and Data Memory

58 OMAP3.2 Subsystem
T
N cycles
M
-
Multiplexed mode is enabled when the MAD bit field in CS configuration
register is set to 1 (see Table 19).
Read address
D0
00
D1 Î Î Î Î Î D1
SPRU749A