Omap3.2 Features - Texas Instruments OMAP5912 Reference Manual

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OMAP3.2 Features

SPRU749A
The OMAP3.2 includes the following features:
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ARM926EJS megacell including:
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ARM926EJS, running at a maximum frequency of 192 MHz
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MMU with translation lookaside buffer (TLBx)
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L1 16K-byte, four-way, set-associative instruction cache
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L1 8K-byte, four-way, set-associative data cache with write buffer
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MPU interrupt handler level 1
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Embedded trace macrocell module, ETM version 2.a in a 13-bit mode
configuration or in a 17-bit demultiplexed mode configuration
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DSP megacell rev 2.0a+ including:
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Embedded ICE emulator interface through JTAG port
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TMS320C55x (C55x) DSP rev 2.1, running at a maximum of 192 MHz
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L1 cache (24K bytes)
H
16K-byte, two-way, set-associative instruction cache (on the
OMAP5912 prototype, one wait state is introduced in case of
discontinuity)
H
2 X 4K-byte RAM set for instruction
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DARAM 64K-byte, zero wait state, 32-bit organization
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SARAM 96K-byte, zero wait state, 32-bit organization
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PDROM (32K bytes)
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DMA controller: six physical channels, five ports
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DSP trace module
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Hardware accelerators motion estimation (ME), discrete/inverse
discrete cosine transform (DCT/IDCT), and pixel interpolation (PI)
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DSP interrupt handler level 1 in the C55x DSP core
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DSP MMU
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DSP level 2 interrupt handler, which enables connection to 16 additional
interrupt lines outside OMAP. The priority of each interrupt line is
controlled by software.
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DSP interrupt interface, which enables connection to the interrupt lines
coming out of the level 2 interrupt handler and the interrupt lines requiring
OMAP3.2 Features
OMAP3.2 Subsystem 21