Write Access Size Adaptation And Cs Pulse Width High Control - Texas Instruments OMAP5912 Reference Manual

Figure 17. Asynchronous 16-Bit Write Operation on 16-Bit Multiplexed Address and Data
Memory With Ready (WELEN = 2, WRWST = 0, FCLKDIV = 0)
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A/D(15:0)/
FLASH.A(25:16)
FLASH.WE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
READY_SYNC2

Write Access Size Adaptation and CS Pulse Width High Control

SPRU749A
M
VA
-
During write access, the EMIFS splits the Word32 access into two Word16
accesses in case of 16-bit device width. 4xWord32 burst write are split into
8 successive Word16 accesses. The split process follows the little endian
protocol (Word32 LSB part at lower Word16 address).
-
During split write accesses and during burst write accesses, the CS signal
is not deactivated unless BTMODE in the Advanced CS configuration
register is set (see Table 28). When BTMODE is set the CS pulse width
high time can be controlled by the BTWST field in the CS configuration
register, Table 19 (see also bus turn around and CS negation time control).
J
CS pulse width high= (BTWST +1) TC_CK
-
This applicable to both multiplexed and non-multiplexed access modes.
Low
Write data
00
OMAP3.2 Subsystem
Traffic Controller
Q
51