Mode 4 And Mode 5 Synchronous Burst Read Operation Mode; Synchronous Read In Non-Multiplexed Address And Data Memory - Texas Instruments OMAP5912 Reference Manual

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Mode 4 and Mode 5 Synchronous Burst Read Operation Mode

Mode 4 Synchronous Burst 4x16-Bit Read Operation on 16-Bit Width Device

(RDWST=3, FCLKDIV =0, ADVHOLD=0, RDMODE=4). Data write-back on the bus after

read completion.

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

The synchronous burst read mode 4 and 5 are selected by setting the

RDMODE bit field in the corresponding EMIFS chip-select configuration

RDMODE = 4 or 5

This mode only supports synchronous read accesses (single or

consecutive). Flash devices usually require synchronous setup and

enable mode to be done after power up. RDMODE must be changed to

mode 4 or mode 5 only after flash device setup.

The REF_CLK is divided from TC_CK by a programmable value

contained in FCLKDIV bit field of the CS configuration register (see

CS, ADV and address are driven one REF_CLK cycle before the first

FLASH.CLK rising edge is provided externally. This ensures CS, ADV, and

address valid setup time to device clock rising edge to be met.

Valid address

OMAP3.2 Subsystem

Traffic Controller

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