Ocp-T1/Ocp-T2 - Texas Instruments OMAP5912 Reference Manual

Figure 2. Traffic Controller Functional Block Diagram
Slow
16,32
memory
I/F
Slow bus
Fast
16
memory
I/F
Fast bus
L3
32
OCP
T1
OCP
I/F
target-1
L3
32
OCP
T2
OCP
I/F
target-2
L3
32
OCP
I
OCP
I/F
initiator
3.1

OCP-T1/OCP-T2

SPRU749A
WT
WT
WT
WT
The OMAP 3.2 hardware provides two identical general-purpose ports for the
connection of custom peripherals or memory subsystems. These ports can be
accessed by all the initiators mentioned in the previous sections.
Each port arbitrates between all initiator requests and allows atomic
transactions for the MPU, for the DSP, and for the external initiator to
implement semaphore-based synchronization schemes between software
tasks (running either on the same CPU or on two different CPUs).
Slow bus I/F
arbiter
Fast bus I/F
arbiter
Multi-
OCP-T1 I/F
banks
arbiter
EMIFS DMA
EMIFF DMA
OCP-T1 DMA
OCP-T2 DMA
OCP-T2 I/F
arbiter
Window tracer
Control and
configuration
32
OMAP3.2 Subsystem
Traffic Controller
DSP
32
MMU
bus
DSP bus
I/F
32
EMIFS DMA
32
System
DMA
EMIFF DMA
control
32
I/F
OCP-T1
32
DMA
EMIFS DMA
32
MPU
bus
MPU bus
I/F
TIPB
27