Write Access In Mode 7 - Texas Instruments OMAP5912 Reference Manual

Write Access in Mode 7

Figure 32. Mode 7 Asynchronous Two Successive 16-Bit Write Operations on a 16-Bit
Width Device (WRWST=0, WELEN=0 FCLKDIV=1 and ADVHOLD=0)
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A(25:1)
FLASH.D(15:0)
FLASH.WE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY
SPRU749A
during read access in mode 7. RDWST field is not active and FLASH.RDY
is not monitored in this mode (non-full-handshaking mode only).
-
CS, ADV, OE are driven low for the entire access. ADVHOLD, OESETUP,
OEHOLD time control are disabled in this mode.
-
Address and data multiplexed protocol is not supported in mode 7 (MAD
bit field not considered).
-
One TC_CK cycle after access completion (CS high) the data bus is driven
with the previous read value.
-
Figure 32 shows FLASH.CLK activation details during a write access in
mode 7. Below example shows two successive write accesses with
minimum access time.
M
Add0
D0
N
P
N
Q
00
OMAP3.2 Subsystem
Traffic Controller
M
Add1
D1
P
Q
67