Multiplexed Asynchronous Write Operation - Texas Instruments OMAP5912 Reference Manual

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Multiplexed Asynchronous Write Operation

Asynchronous 16-Bit Write Operation on a Multiplexed Address/16-Bit Data

Bus (WRWST=1, WELEN=3 , FCLKDIV=00 and ADVHOLD=0)

FLASH.A/D(15:0)/

FLASH.A(25:16)

FLASH.BE(1:0)

The CS address and data hold time setup from WE high is fixed to one

REF_CLK (Q cycle in Figure 14).

In asynchronous mode 0−1−2−3, REF_CLK is not provided outside the

EMIFS and FLASH.CLK is kept low. In synchronous mode 4−5, REF_CLK

is provided outside the EMIFS through the FLASH.CLK (see mode 4,5).

In synchronous mode 7, REF_CLK is inverted and provided outside the

EMIFS through FLASH.CLK (see mode 7).

Figure 15 shows a timing diagram with multiplexed address/data bus.

Multiplexed mode is enabled when MAD bit field in CS configuration

Address drive time follows CS activation (no setup time guaranty).

Address setup time to ADV rising edge is controlled by ADVHOLD.

Address invalid from ADV rising edge is guaranteed to be minimum one

REF_CLK cycle.

OMAP3.2 Subsystem

Traffic Controller

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