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3.2.3
EMIFS Miscellaneous Memory Signal Control
3.2.4
EMIFS Configuration
3.2.5
EMIFS Abort Control
3.2.6
EMIFS External Device Connections
3.2.7
EMIFS Address Mapping and Data Control in Multiplexed Mode
SPRU749A
the device type is emulation then BM resets to 1. Otherwise, BM resets to 0.
Thus, the boot is executed from CS0 or from CS3 attached memories. During
normal execution, BM can be changed dynamically but obvious software
precautions are required to prevent system crash.
Common flash memory supports the write protection, WP, input pin
(FLASH.WP on ball V4) to prevent erroneous write access sequence to
corrupt their content. EMIFS interface includes WP output pin and provides full
software control of it.
Common flash memory supports the RESET input pin to allow device state
machine to be properly reset on power up and also to minimize power
consumption in idle mode. The EMIFS interface includes a FLASH.RP (on ball
W1) output pin and provides software and hardware control of it.
EMIFS control and configuration can be done dynamically. EMIFS ensures
that a new CS configuration takes effect only when no access is requested (CS
idle). To prevent inconsistency and critical behavior, the EMIFS configuration
must be done by MPU software while other masters are inactive.
In case of access restriction violation, and in case of access time-out errors,
the EMIFS can handle an interrupt line and abort status register to allow abort
events system monitoring.
Please refer to Chapter 9 for a detailed description of the EMIFS device
connections.
-
In order to minimize the number of IC pins for external memory
connection, the EMIFS can support multiplexed address and data
memory devices without adding external logic.
-
Selection of the multiplexed mode is done through the MAD bit in the CS
configuration register. Multiplexed mode is only available in the following
modes:
J
Mode 0 asynchronous read and write
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OMAP3.2 Subsystem
33
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