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Static NVM Settings
Register Name
Field Name
RAIL_SEL_2
BUCK5_GRP_SEL
LDO1_GRP_SEL
LDO2_GRP_SEL
LDO3_GRP_SEL
RAIL_SEL_3
VMON2_GRP_SEL
VMON1_GRP_SEL
LDO4_GRP_SEL
VCCA_GRP_SEL
FSM_TRIG_SEL_1
MCU_RAIL_TRIG
SOC_RAIL_TRIG
OTHER_RAIL_TRIG
SEVERE_ERR_TRIG
FSM_TRIG_SEL_2
MODERATE_ERR_TRI
G
5.8 Interrupt Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
2
changed though I
C after startup.
Register Name
Field Name
FSM_TRIG_MASK_1
GPIO1_FSM_MASK
GPIO1_FSM_MASK_P
OL
GPIO2_FSM_MASK
GPIO2_FSM_MASK_P
OL
GPIO3_FSM_MASK
GPIO3_FSM_MASK_P
OL
GPIO4_FSM_MASK
GPIO4_FSM_MASK_P
OL
FSM_TRIG_MASK_2
GPIO5_FSM_MASK
GPIO5_FSM_MASK_P
OL
GPIO6_FSM_MASK
GPIO6_FSM_MASK_P
OL
GPIO7_FSM_MASK
GPIO7_FSM_MASK_P
OL
GPIO8_FSM_MASK
GPIO8_FSM_MASK_P
OL
18
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
Table 5-8. FSM NVM Settings (continued)
TPS6594141B-Q1
Value
Description
0x2
SOC rail group
0x1
MCU rail group
0x2
SOC rail group
0x1
MCU rail group
0x2
SOC rail group
0x1
MCU rail group
0x2
MCU power error
0x3
SOC power error
0x3
SOC power error
0x0
Immediate shutdown
0x1
Orderly shutdown
Table 5-9. Interrupt NVM Settings
TPS6594141B-Q1
Value
Description
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
Copyright © 2022 Texas Instruments Incorporated
LP876441B1-Q1
Value
Description
0x0
No group assigned
0x0
No group assigned
0x1
MCU rail group
0x2
MCU power error
0x3
SOC power error
0x3
SOC power error
0x0
Immediate shutdown
0x1
Orderly shutdown
LP876441B1-Q1
Value
Description
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022
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