Emifs Memory Timing Control - Texas Instruments OMAP5912 Reference Manual

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Traffic Controller

EMIFS Memory Timing Control

OMAP3.2 Subsystem

Mode 0. Asynchronous read. Used for any asynchronous memory,

including flash devices.

Mode 1−2−3. Asynchronous page mode read with control of 4

(mode1), 8 (mode 2), 16 (mode 3) words (device width) per page.

These modes are mainly used for page mode flash devices.

Mode 4−5. Synchronous burst read (with burst advance control for

mode 4). These modes are mainly used for synchronous burst flash

Mode 7. Synchronous pipelined burst read. This mode is mainly used

for TI embedded IC ROM and RAM memories.

For all these modes write accesses are performed according to asynchro-

nous write protocol.

Single and burst access address alignment

OMAP master only issues Word16 and Word32 aligned access (word

address must be aligned on word size address boundary).

OMAP master only issues linear, incrementing, and fixed size

4xWord32 access bursts. Burst access is aligned on burst size

address boundary (starting burst LSB address A[0−3] is always equal

to [0000]). External devices like synchronous flash memory may

require a burst protocol programming to conform to the EMIFS burst

In both asynchronous and synchronous modes, all EMIFS to memory

control signals are controlled with an EMIFS internal reference clock

(REF_CLK) which is the TC_CK divided down. Depending on the CS

configuration, this internal clock can be available outside through the

FLASH.CLK (ball N3) output pin.

The REF_CLK is divided from TC_CK (traffic controller clock, see

section 4.2.5) by a programmable value contained in FCLKDIV bit

field of the CS configuration register, Table 19. This accommodates

the timing constraints of slow devices, even with high system clock

In asynchronous mode 0−1−2−3, the FLASH.CLK (ball N3) is low.

In synchronous mode 4−5−7, REF_CLK is available through FLASH.CLK.

This is also the case during asynchronous write access. FLASH.CLK

clock is connected to the external synchronous device input clock

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