General Description; Emifs Synchronous And Asynchronous Modes - Texas Instruments OMAP5912 Reference Manual

3.2.1

General Description

EMIFS Synchronous and Asynchronous Modes

SPRU749A
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Each chip-select controls an address range of 64M bytes with dedicated
configuration registers to fulfill the protocol and the timing constraints
compliant with the external device associated with it. Each chip-select
configuration register supports dynamic configuration.
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CS0 and CS3 address mapping can be swapped with the BM bit in the
EMIFS configuration (EMIFS_CONFIG) register.
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The EMIFS can support 16-bit interface width only. Based on the CS
configuration, the interface adjusts the access size (splitting word32)
according to external device attached to the CS. User must refer to the
IC device documentation for the external device width supported by
the IC (16-bit width only or 16-bit and 32-bit width).8-bit device width
is not supported without adding external logic.
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The EMIFS can control multiplexed address and data memory devices
without adding external logic based on CS configuration. The multiplexing
scheme is supported for synchronous and asynchronous access mode.
Both multiplexed and non-multiplexed devices can be supported with the
same IC on different chip-selects (embedded IC non-multiplexed
memories and external multiplexed devices).
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The EMIFS behavior conforms to the little endian protocol.
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The EMIFS supports 8-,16-, or 32-bit asynchronous and synchronous
read, 4- x 32-bit synchronous burst read and 8-, 16-, or 32-bit
asynchronous write.
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The EMIFS boot configuration is controlled by dedicated pins that are
sampled at IC reset time. This provides flexible boot CS and configuration
selection.
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The EMIFS is a multimaster memory interface. It supports flexible and
programmable arbitration protocol (LRU priority ordering or dynamic time
based priority ordering).
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The EMIFS includes a programmable time-out timer to prevent system
hanging with nonresponding devices. Automatic access completion with
interrupt and status logging are issued on time out events.
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The EMIFS supports dynamic local idle mode control. The EMIFS also
supports IC deep power-down mode request synchronization.
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The operation mode of the EMIFS for a given chip-select region is selected
by the RDMODE bit field of the CS configuration registers. Operations
supported are:
Traffic Controller
OMAP3.2 Subsystem 29