Table of Contents
Advertisement
Static NVM Settings
Register Name
Field Name
RAIL_SEL_1
BUCK1_GRP_SEL
BUCK2_GRP_SEL
BUCK3_GRP_SEL
BUCK4_GRP_SEL
RAIL_SEL_2
BUCK5_GRP_SEL
LDO1_GRP_SEL
LDO2_GRP_SEL
LDO3_GRP_SEL
RAIL_SEL_3
LDO4_GRP_SEL
VCCA_GRP_SEL
FSM_TRIG_SEL_1
MCU_RAIL_TRIG
SOC_RAIL_TRIG
OTHER_RAIL_TRIG
SEVERE_ERR_TRIG
FSM_TRIG_SEL_2
MODERATE_ERR_TRI
G
5.8 Interrupt Settings
These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
2
changed though I
C after startup.
Register Name
Field Name
FSM_TRIG_MASK_1
GPIO1_FSM_MASK
GPIO1_FSM_MASK_P
OL
GPIO2_FSM_MASK
GPIO2_FSM_MASK_P
OL
GPIO3_FSM_MASK
GPIO3_FSM_MASK_P
OL
GPIO4_FSM_MASK
GPIO4_FSM_MASK_P
OL
FSM_TRIG_MASK_2
GPIO5_FSM_MASK
GPIO5_FSM_MASK_P
OL
GPIO6_FSM_MASK
GPIO6_FSM_MASK_P
OL
GPIO7_FSM_MASK
GPIO7_FSM_MASK_P
OL
GPIO8_FSM_MASK
GPIO8_FSM_MASK_P
OL
24
Optimized TPS65941213-Q1 and TPS65941111-Q1 PMIC User Guide for
Jacinto™ 7 J721E, PDN-0C
Table 5-7. FSM NVM Settings
TPS65941213-Q1
Value
Description
0x2
SOC rail group
0x2
SOC rail group
0x1
MCU rail group
0x1
MCU rail group
0x2
SOC rail group
0x1
MCU rail group
0x1
MCU rail group
0x2
SOC rail group
0x1
MCU rail group
0x1
MCU rail group
0x2
MCU power error
0x3
SOC power error
0x1
Orderly shutdown
0x0
Immediate shutdown
0x1
Orderly shutdown
Table 5-8. Interrupt NVM Settings
TPS65941213-Q1
Value
Description
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
Copyright © 2022 Texas Instruments Incorporated
TPS65941111-Q1
Value
Description
0x2
SOC rail group
0x2
SOC rail group
0x0
No group assigned
0x0
No group assigned
0x2
SOC rail group
0x0
No group assigned
0x2
SOC rail group
0x2
SOC rail group
0x2
SOC rail group
0x1
MCU rail group
0x2
MCU power error
0x3
SOC power error
0x1
Orderly shutdown
0x0
Immediate shutdown
0x1
Orderly shutdown
TPS65941111-Q1
Value
Description
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x0
Not masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
0x1
Masked
0x0
Low; Masking sets signal
value to '0'
SLVUC99A – JANUARY 2022 – REVISED JANUARY 2022
Submit Document Feedback
www.ti.com
Advertisement
Table of Contents
