Emifs Cs0 And Cs3 Decoding Control - Texas Instruments OMAP5912 Reference Manual

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3.2.2

EMIFS CS0 and CS3 Decoding Control

32 OMAP3.2 Subsystem
pin (FLASH.RDY on ball V2) can also be used in combination with internal
wait state (full-handshaking mode).
J
In non-full-handshaking mode, the RDWST and PGWST (mode
1−2−3 only) bit field in CS configuration register are used to control
internal read wait state generation.
J
In non-full-handshaking, the WELEN bit field in CS configuration
register is used to control internal write wait state generation.
J
In full-handshaking mode, FLASH.RDY is monitored by the EMIFS to
control read and write access time. The access is completed when
both the internal wait state has expired and FLASH.RDY is asserted
by the external device. The FLASH.RDY assertion/deassertion timing
constraint depends on synchronous or asynchronous access mode.
J
Modes 0−4−5
Full-handshaking support on particular CS can be disabled for these
modes through the dynamic wait state register.
Modes 1−2−3−7 always follow the non-full-handshaking protocol and
FLASH.RDY is never monitored in these modes, even if the full-hand-
shaking bit field in the dynamic wait state register is cleared.
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To prevent data bus contention when slow devices are attached to the IC,
the BTWST bit field in the CS configuration register is used to control
TC_CK cycle idle time between specific access sequences.
-
The BTMODE field in the advance CS configuration register extends the
previous mode. The BTWST bit field controls the CS negation time
between successive accesses to the same CS.
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To prevent data bus floating when no access is requested at the interface
(idle sequence), the EMIFS keep the data bus driven with the previous
written data or read data (bus keeping feature). In case of read to idle
sequence, the delay time from read to write-back is at least one TC_CK
cycle or controlled by BTWST (TC_CK ) cycles.
-
If dynamic Wait state mode is used, then one REF_clk cycle must be
added to all of the formulas describing CS and ADV width in this section.
CS0 and CS3 address decoding (address in the TC memory mapping) can be
swapped through the BM bit field in the EMIFS global control register. When
the BM bit field is set, CS3 is activated in the 0000:0000−03FF:FFFF range
and CS0 is activated in the 0C00:0000−0FFF:FFFF range. The BM bit is
sampled at reset depending on two factors. If MPU_BOOT (ball J20) is 1 and
are by default in full-handshaking mode.
SPRU749A