Traffic Controller - Texas Instruments OMAP5912 Reference Manual

3

Traffic Controller

SPRU749A
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Two DPLLs:
OMAP3.2 provides one DPPL per main clock domain:
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MPU/traffic controller clock domain
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DSP clock domain
The OMAP3.2 gigacell enables the software to define either:
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Two coupled domains in scalable mode: only one DPLL is active. The
other clocks are a multiple of it.
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Mixed mode: only one domain is working in asynchronous mode. The
other domains are in scalable mode.
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Endianism conversion for DSP
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The DSP uses big-endian format, whereas the MPU uses little-endian
format. Also, as a rule, the OMAP5912 chip works in little endian.
Thus, the endianism conversion is useful for all memory or peripheral
accesses from on-chip peripherals or all shared memories to the DSP
megacell.
OMAP 3.2 is considered a subchip of OMAP5912. To connect the OMAP
peripherals, six buses are provided:
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MPU shared TIPB
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MPU private TIPB
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DSP shared TIPB
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DSP private TIPB
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OCP-T2
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OCP-I
The OMAP 3.2 traffic controller (TC) is the central interconnect that manages
all accesses between the following:
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OMAP internal initiators and target resources
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OMAP external initiators and target resources
The TC can have its own clock domain or be synchronous to the MPU clock
domain. See Chapter 4, Clocks, for more details on clock domains. Typically,
the TC clock runs at half of the MPU and DSP clocks.
System initiators are:
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MPU. The MPU is connected to the TC using the MPU bus. The MPU can
access memory devices or other type of targets connected to OCP-T1,
Traffic Controller
OMAP3.2 Subsystem 25