Interrupt Settings - Texas Instruments TPS65941515-Q1 User Manual

Powering jacinto 7 j7200 dra821 with single tps6594-q1 pmic, pdn-2a
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5.8 Interrupt Settings

These settings detail the default configurations for what is monitored by nINT pin. All these settings can be
2
changed though I
C after startup.
Register Name
FSM_TRIG_MASK_1
FSM_TRIG_MASK_2
FSM_TRIG_MASK_3
MASK_BUCK1_2
MASK_BUCK3_4
MASK_BUCK5
SLVUCD4 – NOVEMBER 2022
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Table 5-8. Interrupt NVM Settings
Field Name
GPIO1_FSM_MASK
GPIO1_FSM_MASK_POL
GPIO2_FSM_MASK
GPIO2_FSM_MASK_POL
GPIO3_FSM_MASK
GPIO3_FSM_MASK_POL
GPIO4_FSM_MASK
GPIO4_FSM_MASK_POL
GPIO5_FSM_MASK
GPIO5_FSM_MASK_POL
GPIO6_FSM_MASK
GPIO6_FSM_MASK_POL
GPIO7_FSM_MASK
GPIO7_FSM_MASK_POL
GPIO8_FSM_MASK
GPIO8_FSM_MASK_POL
GPIO9_FSM_MASK
GPIO9_FSM_MASK_POL
GPIO10_FSM_MASK
GPIO10_FSM_MASK_POL
GPIO11_FSM_MASK
GPIO11_FSM_MASK_POL
BUCK1_ILIM_MASK
BUCK1_OV_MASK
BUCK1_UV_MASK
BUCK2_ILIM_MASK
BUCK2_OV_MASK
BUCK2_UV_MASK
BUCK3_ILIM_MASK
BUCK3_OV_MASK
BUCK3_UV_MASK
BUCK4_OV_MASK
BUCK4_UV_MASK
BUCK4_ILIM_MASK
BUCK5_ILIM_MASK
BUCK5_OV_MASK
BUCK5_UV_MASK
User Guide for Powering Jacinto
Copyright © 2022 Texas Instruments Incorporated
TPS65941515-Q1
Value
Description
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x1
Masked
0x0
Low; Masking sets signal value to '0'
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
0x0
Interrupt generated
TM
7 J7200 DRA821 with Single TPS6594-Q1
Static NVM Settings
19
PMIC, PDN-2A

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