Read Access Size Adaptation And Cs Pulse Width High Control - Texas Instruments OMAP5912 Reference Manual

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Read Access Size Adaptation and CS Pulse Width High Control

Asynchronous 32-Bit Read Operation on a 16-Bit Width Device. RDWST=4

FCLKDIV=0 OESETUP = 0 OEHOLD = 0 ADVHOLD = 0 BTWST=0 BTMODE=0. Data

write-back on the bus after read completion.

FLASH.A(25:1)

FLASH.D(15:0)

FLASH.BE(1:0)

OMAP3.2 Subsystem

In read mode 0, the EMIFS splits the Word32 access into two Word16

accesses in case of 16-bit device width. 4xWord32 burst read are split into

eight successive Word16 accesses. The split process follows the little

endian protocol (Word32 LSB part at lower Word16 address).

During split read accesses and during burst read accesses, the CS signal

is deactivated for at least one TC_CK between two successive accesses.

CS pulse-width high time can be extended by the BTWST field in the CS

configuration register (see also bus turn around and CS negation time

CS pulse width high = (BTWST +1) TC_CK

Valid address 0

Valid address 1

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