Advanced Oe Control - Texas Instruments OMAP5912 Reference Manual

Figure 5. Asynchronous 16-Bit Read Operation on a 16-Bit Width Device. RDWST=0
FCLKDIV=0 OESETUP=0 OEHOLD=0 ADVHOLD=0. Data write-back on the bus after
read completion.
TC_CLK
REF_CLK
FLASH.CLK
FLASH.CSx
FLASH.ADV
FLASH.A(25:1)
FLASH.D(15:0)
FLASH.OE
FLASH_DIR_O
FLASH.BE(1:0)
FLASH.RDY

Advanced OE Control

SPRU749A
M cycles
OESETUP cycles
-
OE activation delay time from CS and address valid is programmable
through OESETUP bit field in the advanced CS configuration register.
Activation delay timing is equal to:
J
(OESETUP) REF_CLK (OESETUP cycles in Figure 6).
-
OE deactivation advance time to CS and address invalid is programmable
through OEHOLD bit field in the advanced CS configuration register.
Deactivation advance timing is equal to:
J
(OEHOLD) REF_CLK (OEHOLD cycles in Figure 6).
-
Because CS minimum pulse width is 2 REF_CLK the OE delay and
advance timing value must be set so:
J
(OESETUP + OEHOLD) is inferior or equal to RDWST. Noncompliant
programming ends up with bad access completion.
Low
N cycles
Valid address
00
OMAP3.2 Subsystem
Traffic Controller
Valid data D0 D0
37