Write Access In Mode 4 And 5 - Texas Instruments OMAP5912 Reference Manual

Multimedia processor device overview and architecture

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Mode 5 Synchronous Burst 8x16-Bit Read Operation on Multiplexed

Address/Data 16-Bit Width Device (RDWST=3, FCLKDIV =0, ADVHOLD=0, OESETUP =

3, RDMODE=5). Data write-back on the bus after read completion.

FLASH.A(25:16)

FLASH.A.D(15:0)

FLASH.BE(1:0)

Write Access in Mode 4 and 5

Figure 27 shows FLASH.CLK activation details during a write access in

mode 5 (non-multiplexed). Same behavior for the multiplexed address

and data protocol.

OMAP3.2 Subsystem

Traffic Controller

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