Interrupt Operation; Interrupt Control Modes And Interrupt Operation - Hitachi H8S/2678 Series Reference Manual

3.5

Interrupt Operation

3.5.1

Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2678 Series differ depending on the interrupt control mode.
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 3.6 shows the interrupt control modes.
The interrupt controller performs interrupt control according to the interrupt control mode set by
the INTM1 and INTM0 bits in INTCR, the priorities set in IPR, and the masking state indicated by
the I bit in the CPU's CCR, and bits I2 to I0 in EXR.
Table 3.6 Interrupt Control Modes
INTCR
Interrupt
Control
Mode INTM1
0 0
—
2 1
—
74
Priority
Setting
INTM0 Registers
0 —
1 —
0 IPR
1 —
Interrupt
Mask Bits Description
I Interrupt mask control is performed by
the I bit.
— Setting prohibited
I2 to I0 8-level interrupt mask control is
performed by bits I2 to I0.
8 priority levels can be set with IPR.
— Setting prohibited