Interrupt Operation; Interrupt Handling Process - Hitachi H8/3048 Hardware Manual

Single-chip microcomputer

Table of Contents

5.4 Interrupt Operation

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The H8/3048 Series handles interrupts differently depending on the setting of the UE bit. When

UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and

UI bits. Table 5-4 indicates how interrupts are handled for all setting combinations of the UE, I,

and UI bits.

NMI interrupts are always accepted except in the reset and hardware standby states. IRQ

interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt

requests are ignored when the enable bits are cleared to 0.

Table 5-4 UE, I, and UI Bit Settings and Interrupt Handling

UE = 1: Interrupts IRQ

masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and

unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure

5-4 is a flowchart showing how interrupts are accepted when UE = 1.

All interrupts are accepted. Interrupts with priority level 1 have higher

No interrupts are accepted except NMI.

All interrupts are accepted. Interrupts with priority level 1 have higher

NMI and interrupts with priority level 1 are accepted.

No interrupts are accepted except NMI.

and interrupts from the on-chip supporting modules can all be