Dtc Vector Register (Dtvecr); Activation Sources - Hitachi H8S/2628 Hardware Manual

8.2.8

DTC Vector Register (DTVECR)

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
Bit Bit Name Initial Value
7 SWDTE 0
6 DTVEC6 0
5 DTVEC5 0
4 DTVEC4 0
3 DTVEC3 0
2 DTVEC2 0
1 DTVEC1 0
0 DTVEC0 0
8.3

Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI_0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, the existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Figure 8.2 shows a block diagram of DTC activation source control. For details, see section 5,
Interrupt Controller.
R/W Description
R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
When the DISEL bit is 0 and the specified
•
number of transfers have not ended
When 0 is written to the DISEL bit after a
•
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended
or when the specified number of transfers have
ended, this bit will not be cleared.
R/W DTC Software Activation Vectors 0 to 6
R/W
These bits specify a vector number for DTC software
R/W
activation.
R/W
The vector address is expressed as H'0400 + (vector
R/W
number × 2). For example, when DTVEC6 to
R/W
DTVEC0 = H'10, the vector address is H'0420. When
R/W
the bit SWDTE is 0, these bits can be written.
Rev. 1.0, 09/02, page 103 of 568