Timer Output Control Register (Tocr) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

8.2.6 Timer Output Control Register (TOCR)

TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit
Initial value
Read/Write
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4
XTGD Description
0 Input capture A in channel 1 is used as an external trigger signal in complementary
PWM mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in the timer output master enable register
(TOER) are cleared to 0, disabling ITU output.
1 External triggering is disabled
7 6
— —
1 1
— —
Reserved bits
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
5 4
— XTGD
1 1
— R/W
Reserved bits
3 2
— — OLS4
1 1
—
— R/W
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
1 0
OLS3
1 1
R/W
(Initial value)
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