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8.2.2
EEPROM Protection Register (EPR)
Bit:
Initial value:
Read/Write:
EPR is an 8-bit register that enables the writing of EEPROM write/erase protect bits.
Bit 7—Protect Bit Mode (PBM): This bit selects the EEPROM data area or protection area.
The protection area is selected when the PBM bit is cleared to 0. The data area is selected when
the PBM bit is set to 1.
Writing the PBM bit automatically sets both the OC1 and OC0 bits in ECR to 1, disabling writing
or erasing of the EEPROM. At the end of a write or erase operation in the protection area, the
PBM bit itself is automatically set to 1, selecting the data area.
The protect bits are allocated at the same addresses as the first bytes of the pages in the EEPROM
data area. Each page of the EEPROM can be protected individually.
See section 8.5, Write/Erase Protection, for further information on the protection area and data
area.
Bit 7: PBM
Description
0
Protection area is selected
1
Data area is selected
Bits 6 to 0—Reserved: Always read as 1 and cannot be written to.
Although not used at present, reserved bits may be used in the future. When writing to EPR, write
0 to these bits.
ECR and EPR are initialized by the SLEEP instruction. After clearing sleep mode, software must
set up these registers again before writing to EEPROM.
8.3
EEPROM Read Operation
The EEPROM is read directly by the CPU, using the same instructions as for reading ROM or
RAM. The read data is sent to the CPU via a 16-bit bus. If word access is performed at an odd
address, the word at the preceding even address is read.
7
6
PBM
—
1
1
R/W
R
5
4
3
—
—
—
1
1
1
R
R
R
2
1
0
—
—
—
1
1
1
R
R
R
(Initial value)
83
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