Multiprocessor Communication - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Figure 11-8 shows an example of SCI receive operation in asynchronous mode.
Start
1
bit
0
RDRF
FER
Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)

11.3.3 Multiprocessor Communication

The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending
cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 11-9 shows an example of communication among different processors using a
multiprocessor format.
Parity
Data
bit
D0 D1 D7 0/1
1 frame
Stop Start
bit bit
1
0 D0 D1
RXI RXI interrupt handler
request reads data in RDR and
clears RDRF flag to 0
Parity Stop
Data
bit bit
D7 0/1 1
Framing error,
ERI request
1
Idle (mark)
state
365