Interrupt Handling Flowchart - Hitachi H8/500 Series Hardware Manual

Address
error?
Y
Address
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Program execution state
Interrupt requested?
N
N
Trace?
N
NMI?
Y
Level-7 interrupt?
Y
Exception-handling
sequence
Clear T bit
N
Trace
N
error?
Update mask level
Y
To user-coded
exception-handling
routine
Figure 5-2 Interrupt Handling Flowchart
N
Y
N
Level-6 interrupt?
Y
Mask level
Mask level
≤
≤
in SR
in SR 6?
N
Y
Interrupt remains pending
Y
Data transfer
enabled?
N
Save PC
Y
Maximum
mode?
Save PC
N
Save SR
Read destination address
Vectoring
Y
106
N
Level-1 interrupt?
Y
Y
Mask level
5?
in SR = 0?
N
Y
Y
Start DTC
Read DTC vector
Read transfer mode
Read source address
Read data
Source
Y
address increment
mode?
Increment source
N
address (+1 or +2)
Write source address
Write data
Y
Destination
address increment
mode?
Increment source
N
address (+1 or +2)
Write destination
address
Read DTCR
→
DTCR-1 DTCR
Write DTCR
N
DTCR = 0?
N
N