Chain Transfer - Hitachi H8S/2338 Series Hardware Manual

6.3.8

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS
bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR,
DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Figure 6-9 shows the memory map for chain transfer.
DTC vector
Register information
address
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
222
start address
Figure 6-9 Chain Transfer Memory Map
Register information
CHNE = 1
Register information
CHNE = 0
Source
Destination
Source
Destination