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22.4.9
Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 22-6.
In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER
and SCRX).
Table 22-6 Register Configuration
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register FLPWCR *
Serial control register X
Notes: *1 Lower 16 bits of the address.
*2 To access these registers, set the FLSHE bit to 1 in serial control register X. Even if
FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is
disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the
FWE bit in FLMCR1 is not set to 1.
*3 When a high level is input to the FWE pin, the initial value is H'80.
*4 When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 is not set, these registers are initialized to H'00.
*5 FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.
Use byte access on these registers.
22.5
Register Descriptions
22.5.1
Flash Memory Control Register 1 (FLMCR1)
Bit:
Initial value:
R/W:
Note: * Determined by the state of the FWE pin.
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when
FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is
entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the
Abbreviation
FLMCR1 *
FLMCR2 *
EBR1 *
EBR2 *
RAMER *
SCRX
7
6
FWE
SWE1
ESU1
—*
0
R
R/W
R/W
R/W
R/W *
5
2
R *
5
2
R/W *
5
2
R/W *
5
2
5
R/W
R/W *
5
2
R/W
5
4
3
PSU1
EV1
0
0
0
R/W
R/W
Address *
Initial Value
H'00 *
3
H'FFA8
H'00
H'FFA9
H'00 *
4
H'FFAA
H'00 *
4
H'FFAB
H'00
H'FEDB
H'00 *
4
H'FFAC
H'00
H'FDB4
2
1
PV1
E1
0
0
R/W
R/W
1
0
P1
0
R/W
907
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