Chapter 10 Delayed Interrupt Generation Module; Outline; Block Diagram; Registers And Register Details - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Chapter 10:
Delayed Interrupt Generation Module

10.1 Outline

The delayed interrupt generation module generates interrupts for switching tasks for development on a
real-time operating system (REALOS series). The module can be used to generate softwarewise
generates hardware interrupt requests to the CPU and cancel the interrupts.
This module does not conform to the extended intelligent I/O service (EI

10.2 Block Diagram

Figure 10.2a Block diagram of Delayed Interrupt Generation Module

10.3 Registers and Register Details

Delayed interrupt cause issuance/cancellation register (DIRR: Delayed interrupt request register)
Delayed interrupt cause issuance/cancellation register
Address : 00009F
Read/write
Initial value
DIRR controls issuance and cancellation of delayed interrupt requests. Writing '1' to this register issues a
delayed interrupt request, and writing '0' cancels the delayed interrupt request. Upon a reset, the request is
canceled. Either '0' or '1' can be written to the reserved bit area. To access this register, use the set bit or
clear bit instruction for future expansions.
Delayed interrupt cause issuance/cancellation decoder
7 6 5
— — —
H
(–) (–) (–)
(–) (–) (–)
2
Cause latch
4 3 2
— — —
(–) (–) (–)
(–) (–) (–)
OS).
1 0
Bit number
—
R0
DIRR
(–) (R/W)
(–) (0)