Figure 3.6.2 Block Diagram Of Clock Controller - Fujitsu F2MC-8L MB89620 Series Hardware Manual

3.6 Clocks
3.6.2 Clock Controller
The clock controller contains the following four blocks:
• Oscillator
• Clock controller
• Oscillation stabilization delay time selector (optional)
• Standby control register (STBC)
n Blcok Diagram of Clock Controller
Figure 3.6.2 shows the block diagram of the clock controller.
From timebase timer
F : Source oscillation
C
t : Instruction cycle (divide-by-four source oscillation)
inst
62
CHAPTER 3 CPU
STBC STP SLP SPL RST
Enable
F
C
Oscillator
18
2 /F
C
Oscillation stabiliza-
tion delay time
selector (optional)
14
2 /F
C

Figure 3.6.2 Block Diagram of Clock Controller

— — — —
Divide-by-
two
Divide-by-
Clock
four
controller
Stop of supply to the CPU
Pin state
Sleep mode
Stop mode
Clock for
timebase timer
Supply to the CPU
1 t
inst
Supply to the
peripheral circuits
MB89620 series