Clock Controller; Figure 3.6-4 Block Diagram Of Clock Controller - Fujitsu F2MC-8L Series Hardware Manual

3.6.2

Clock Controller

The clock controller contains the following seven blocks:
• Main clock oscillator
• Subclock oscillator
• System clock selector
• Clock controller
• Oscillation stabilization delay time selector
• System clock control register (SYCC)
• Standby control register (STBC)
Blcok Diagram of Clock Controller
Figure 3.6-4 shows the block diagram of the clock controller.
Subclock control
Subclock
oscillator
Main clock control
Main clock
oscillator
From timebase timer
From watch prescaler
F : Main clock source oscillation
CH
F : Subclock source oscillation
CL
t : Instruction cycle
inst
Main clock oscillator
This oscillator is the oscillation circuit for the main clock. It stops oscillation in main-stop and
subclock modes.

Figure 3.6-4 Block Diagram of Clock Controller

Standby control register (STBC)
STP SLP SPL RST
Enable
System clock selector
Enable
Prescaler
Divide-by-four
Divide-by-eight
Divide-by-16
Divide-by-64
4
2 /F
CH
Oscillation
12
2 /F
CH stabilization
16
2 /F delay time
CH
18
2 /F selector
CH
(optional)
15
2 /F
CL
SCM WT1
TMD
Divide-by-two
Divide-by-two
Selector
Selector
Stop of clock supply to
the CPU
2
WT0 SCS CS1 CS0
System clock control register (SYCC)
Pin state
Stop mode
Sleep mode
Watch mode
Clock for
watch prescaler
Clock for
Timebase timer
Supply to the CPU
Clock
1 t
controller
inst
Supply to the
peripheral circuits
1 t
inst
Clock specification
3.6 Clocks
63