Block Diagram Of Clock Generator - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 5 CLOCKS
5.2

Block Diagram of Clock Generator

The clock generator consists of the following five blocks:
• System clock generator circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Selector for oscillation stabilization wait time
I Block diagram of clock generator
Figure 5.2-1 "Block diagram of clock generator" is a block diagram of the clock generator.
Figure 5.2-1 "Block diagram of clock generator" also includes the standby control circuits and
timebase timer circuit.
RST
Interrupt reset
Clock generator
Sub clock
generator
circuit
Pin
X0A
Pin
X1A
X0
X1
116
Figure 5.2-1 Block diagram of clock generator
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Pin
2
Clock selector
SCLK
Clock
divided
by four
PLL multiplier
SCM MCM WS1 WS0 SCS MCS CS1 CS0
circuit
Clock selection register (CKSCR)
System clock
generator
circuit
Clock
Pin
divided
HCLK
by two
Pin
HCLK : Oscillation clock
MCLK : Main clock
SCLK : Sub clock
Reserved
Pin high-
impedance
control circuit
Internal reset
generator
circuit
CPU intermittent
operation selector
CPU-clock
control circuit
Standby control
circuit
Peripheral
Machine clock
clock control
Cancel waiting time
circuit
to stable oscillation
2
2
Clock
Clock Clock
divided
divided divided
MCLK
by 1024
by two by four
Timebase timer
Pin high-impedance
control
Internal reset
Intermittent cycle selection
CPU clock
Stop and sleep signal
Stop signal
Peripheral clock
Selector for
waiting time
to stable
oscillation
Clock Clock Clock
divided divided divided
by four by four by two
To watchdog timer