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MB90420/5 (A) SERIES F
17.2 Operation of Delayed Interrupt Generate Module
When the CPU writes 1 to the corresponding bit of DIRR using software, the request latch in the delayed
interrupt generate module is set to issue the interrupt request to the interrupt controller.
n Operation of delayed interrupt generate module
When the CPU writes 1 to the corresponding bit of DIRR using software, the request latch in the delayed
interrupt generate module is set to issue the interrupt request to the interrupt controller. When the priority of
another interrupt request is lower than that of this interrupt request or when there is no other interrupt
request, the interrupt controller issues this interrupt request to the CPU of the F
compares the interrupt request with the ILM bit in the processor status (PS) and when the request level is
higher than the ILM bit, the CPU starts the hardware interrupt-processing microprogram at termination of the
instruction being executed. As a result, the interrupt-processing routine for this interrupt is executed. When
0 is written to the corresponding bit of DIRR, inside the interrupt-processing routine, the interrupt factor is
cleared and the task is switched.
Figure 17.2 shows the operation of the delayed interrupt generate module.
Delayed interrupt
generate module
DIRR
n Note on using delayed interrupt generate module
• Delayed interrupt request latch
This latch is set when 1 is written to the corresponding bit of DIRR; it is cleared when 0 is written to the bit.
Consequently, the software must be written so as to clear the request in the interrupt-processing routine.
Otherwise, the re-interrupt processing is started at the return from the interrupt processing.
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
Delayed interrupt controller
WRITE
Another
request
ICR vv
ICR xx
Fig. 17.2 Operation of Delayed Interrupt Generate Module
CMP
NTA
17-4
2
MC-16LX. The CPU
2
F
MC-16LX
CPU
ICR vv
CMP
ICR xx
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