Delayed Interrupt Generation Module - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.12

Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate a task switching interrupt.
Use of this module enables F
Block Diagram of Delayed Interrupt Generation Module
Figure 3.12-1 shows the block diagram of the delayed interrupt generation module.
Figure 3.12-1 Block Diagram of Delayed Interrupt Generation Module
List of Register of Delay Interruption Generation Module
The register configuration of the delayed interrupt generation module {delayed interrupt cause generation/
clear register (delayed interrupt request register (DIRR))} is shown in the following figure.
Figure 3.12-2 Delayed Interrupt Cause Generation/clear Register (DIRR)
bit
00009F
H
: Readable/Writable
R/W
Delay interruption factor generation/release register (DIRR) controls the delay factor generation and
release. Writing "1" to this register generates a delayed interrupt request. Writing "0" to it resets the
request. A reset causes the state cause to remain cleared. Either "0" or "1" may be written to the reserved bit
area. However, it is recommended that the set or clear bit instruction for accessing this register be used,
taking the future extension into account.
110
2
MC-16LX CPU to generate or cancel an interrupt request.
2
F MC-16LX bus
15 14 13
delayed interrupt request generation
/clear decoder
Factor latch
12 11
10 9
8
Initial value
R0
-------0
R/W
B