8.2
16-bit Reload Timer Block Diagram
A block diagram of the reload timer is shown below.
■ Reload Timer Block Diagram
16-bit down counter
(TMR0 to TMR2)
Clock selector
Figure 8.2-1 Block Diagram for Reload Timer
16-bit reload register
(TMRLR0 to TMRLR2)
UF
Count
enable
CSL2
CSL1
CSL0
EXCK
Prescaler
Prescaler
clear
Reload
OUT
CTL
IN CTL
External
CSL2
trigger
selection
CSL1
CSL0
CHAPTER 8 16-BIT RELOAD TIMER
RELD
OUTL
INTE
IRQ
UF
CNTE
TRG
External timer output
TOT1(P70)
TOT2(P71)
PFR7 bit
TO1E ,
TO2E
External trigger input
TIN0(P51)
TIN1(P52)
TIN2(P53)
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