Block Diagram Of 8/16-Bit Ppg Timer - Fujitsu F2MC-16LX Hardware Manual

17.1.1

Block Diagram of 8/16-bit PPG Timer

Block diagram of ch0/ch2/ch4 and ch1/ch3/ch5 of 8/16-bit PPG timer is shown.
Block Diagram of 8/16-bit PPG Timer
Figure 17.1-1 shows the block diagram of ch0/ch2/ch4. Figure 17.1-2 shows the block diagram of channels
1/3/5.
Figure 17.1-1 Block Diagram of 8/16-bit PPG Timer (ch0/ch2/ch4)
Timebase counter output:
divided by 512 of Main clock
L/H selection
Peripheral clock 16 division
Peripheral clock
8 division
Peripheral clock
4 division
Peripheral clock
2 division
Peripheral clock
PCNT (Down counter)
L/H selector
Count clock
selection
PRLL PRLBH
PRLL
PPG0/PPG2/PPG4
Output enabled
PPG0/PPG2/PPG4
Output latch
PEN0
PUF0
PPGC0/PPGC2/PPGC4
(Operation mode control)
CHAPTER 17 8/16-BIT PPG TIMER
PPG0/PPG2/PPG4
S
R Q
IRQ
ch1/ch3/ch5 bollow
PIE0
"L"data bus
"H"data bus
405