Watchdog Timer Control Register (Wdtc) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 10 WATCHDOG TIMER
10.2

Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) displays the activation, clearance, and
reset factor of the watchdog timer.
Watchdog Timer Control Register (WDTC)
Figure 10.2-1 shows the watchdog timer control register (WDTC). Table 10.2-1 describes the function of
each bit of the WDTC register.
bit15
Address
0000A8
H
W
Read only
R Write only
X Undefined
Not used
The previous state is held.
*
Default value
The interval time will be 3.5 to 4.5 times of the count clock (output value from the timebase timer) cycle.
For details, see "10.4 Operations of Watchdog Timer".
222
Figure 10.2-1 Watchdog Timer Control Register (WDTC)
bit8 bit7 bit6
(TBTC)
PONR
R
Interval time select bit (HCLK: 6MHz, SCLK: operating at 32 kHz)
WT1 WT0
WDCS & SCM
0 1
0
1 1
0
0
1
1
1
1 1
0 0
0
1
0 0
0 0
1
1 0
1
HCLK: Oscillation clock
SCLK: Sub-clock
WTE
Starts the watchdog timer
(at first write event after reset)
0
Clears the watchdog timer
(at second write event after reset)
No operation
1
Reset cause bits
PONR WRST
1
X
* 1
* *
* *
bit5 bit4 bit3 bit2 bit1
WRST ERST SRST WTE WT1 WT0
R R R W W
Interval time
Minimum Maximum
Approx. 2.39ms Approx. 3.07ms
Approx. 9.56ms Approx. 12.29ms
Approx. 38.23ms Approx. 49.15ms
Approx. 305.83ms
Approx. 393.22ms
Approx. 0.448s Approx. 0.576s
Approx. 3.584s
Approx. 4.608s
Approx. 7.168s Approx. 9.216s
Approx. 14.336s Approx. 18.432s
Watchdog control bit
SRST
ERST
X
X Power on
* * Watchdog timer
External pin (RST ="L" input)
1 *
RST bit (software reset)
* 1
bit0
Initial value
X-XXX111
B
W
Number of oscillation
clock cycles
± 2
14 11
cycles
2 /HCLK
16 ± 2 13 cycles
2 /HCLK
18 ± 2 15 cycles
2 /HCLK
21 ± 2 18
cycles
2 /HCLK
12 ± 2 9
cycles
2 /SCLK
± 2
15 12
cycles
2 /SCLK
16 ± 2 13
2 /SCLK cycles
17 ± 2 14
cycles
2 /SCLK
Reset cause