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MB90335 Series
10.3
Configuration of Watchdog Timer
The watchdog timer consists of following five blocks.
• Count clock selector
• Watchdog counter (two bits counter)
• Watchdog reset generator circuit
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 10.3-1 shows a watchdog timer block diagram.
Time-base timer mode start
Sleep mode start
Stop mode start
2 divided of HCLK
HCLK: Oscillation clock
●
Count clock selector
Circuit that selects the count clock of the watchdog timer from four types of time-base timer output and
four types of watch timer output. This determines the watchdog reset generation time.
●
Watchdog counter (two bits counter)
2-bit up-counter that uses time-base timer output as the count clock.
●
Watchdog reset generator circuit
Generates a reset signal by an overflow of the watchdog counter.
●
Counter clear control circuit
Clears the watchdog counter and controls operation/stop of the counter.
●
Watchdog timer control register (WDTC)
Activates/clears the watchdog timer and holds the reset occurrence factor.
CM44-10137-6E
Figure 10.3-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR
WRST ERST SRST WTE WT1
2
Watchdog timer
Counter
Counter
clear control
clock
circuit
selector
4
Clear
(Time-base timer counter)
1
2
8
2
2
2
2
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 10 WATCHDOG TIMER
10.3 Configuration of Watchdog Timer
WT0
CLR and
Activation
Over-
Watchdog reset
flow
Watchdog
generation
counter
CLR
9
10
11
12
13
14
15
2
2
2
2
2
2
CLR
to Internal reset
generation circuit
circuit
17
18
16
2
2
2
187
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