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6.2
Configuration of Watchdog Timer
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
I Block Diagram of Watchdog Timer
Generation of reset
Shift to sleep mode
Shift to timebase
timer mode
Shift to clock mode
Shift to stop mode
Main clock
(2 division of HCLK)
Sub clock
SCLK
HCLK Oscillation clock
SCLK Sub clock
Figure 6.2-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
WRST ERST
PONR
Watchdog timer
2
Counter clear
Count clock
control circuit
selector
(Timebase timer counter)
1
2
8
2
2
2
(Clock counter)
1
2
5
2
2
2
WTE
WT0
SRST
WT1
Start up
2-bit
counter
Clear
4
9
10
11
12
13
2
2
2
2
2
2
6
7
8
9
10
2
2
2
2
2
2
CHAPTER 6 Watchdog timer
Clock timer control register (WTC)
WDCS
Watchdog reset
To internal reset
generation
generation circuit
circuit
4
14
16
17
18
2
15
2
2
2
11
12
13
14
15
2
2
2
2
209
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