Configuration Of Watchdog Timer - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 10 WATCHDOG TIMER
10.3

Configuration of Watchdog Timer

The watchdog timer consists of following five blocks.
• Count clock selector
• Watchdog counter (two bits counter)
• Watchdog reset generator circuit
• Counter clear control circuit
• Watchdog timer control register (WDTC)
Block Diagram of Watchdog Timer
Figure 10.3-1 shows a watchdog timer block diagram.
Watch mode start
Timebase timer mode start
Sleep mode start
Hold state start
Stop mode start
2 divided of HCLK
HCLK: Oscillation clock
SCLK: Sub clock
Count clock selector
Circuit that selects the count clock of the watchdog timer from four types of timebase timer output and four
types of watch timer output. This determines the watchdog reset generation time.
Watchdog counter (two bits counter)
2-bit up-counter that uses timebase timer output as the count clock.
Watchdog reset generator circuit
Generates a reset signal by an overflow of the watchdog counter.
224
Figure 10.3-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR WRST ERST SRST WTE WT1
2
Watchdog timer
Counter Counter
clear control clock
circuit selector
Claer
(Timebase timer counter)
1 2 8
2 2 2
HCLK
1 2 8
2
2 2
WT0
WDCS bit of
Watch timer control register (WTC)
SCM bit of
Clock selection register (CKSCR)
CLR and
Activation
Over-
Watchdog reset
Watchdog flow
generation
counter
CLR
4
4
9
10 11 12 13 14
15
2 2
2 2 2 2
2
9
10 11 12 13 14
15
2 2
2 2 2 2 2
CLR
to Internal reset
generation circuit
circuit
18
16 17
2
2 2
18
16 17
2 2
2