Time-Base Timer Mode - Fujitsu MB90335 Series Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5 Standby Mode
6.5.2

Time-base Timer Mode

The time-base timer mode terminates the original oscillation and all the operations
other than the time-base timer and the watch timer, resulting in termination of all the
functions other than the time-base timer and the watch timer.
■ Transition to Time-base Timer Mode
In the PLL clock mode or the main clock mode, writing "0" to the watch/time-base timer mode bit (TMD)
of the low-power consumption mode control register (LPMCR) makes the transition to the time-base timer
mode.
●
Data retention function
In the time-base timer mode, the contents of dedicated registers such as accumulators and the internal RAM
are held unchanged.
●
Operation during an interrupt request
Writing "0" to the TMD bit of the low-power consumption mode control register (LPMCR) does not make
the transition to the time-base timer mode if there is an interrupt request.
●
Pin state
You can set whether the external pin in the time-base timer mode should be retained in the preceding state
or becomes to the high impedance state by controlling the pin state specification bit (SPL) in the LPMCR
register.
■ Cancellation of Time-base Timer Modes
The low-power consumption circuit cancels the time-base timer mode by generating a reset input or an
interrupt request.
●
Return by external reset
The external reset initializes the mode to the main clock mode.
●
Return by interrupt
If there is an interrupt request higher than level 7 from peripheral circuit and others in the time-base timer
mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = 111
control circuit cancels the time-base timer mode. After cancellation of time-base timer modes, the action is
the same as for ordinary interrupt processing. When an interrupt is acceptable according to the setting of
the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt
control register (ICR), interrupt processing is performed. When an interrupt is not acceptable, processing
from the instruction succeeding the one before entering time-base timer mode continues.
Note:
When handling an interrupt, the CPU usually services the interrupt after executing the instruction that
follows the one specifying the time-base timer mode.
148 FUJITSU MICROELECTRONICS LIMITED
MB90335 Series
), the low-power consumption
B
CM44-10137-6E